The present disclosure relates to an electrostatic discharge (ESD) protection circuit.
Electrostatic discharge is an event that can occur during device fabrication, assembly packaging, or device handling. During a typical ESD event, a large amount of charge is accumulated in a bonding pad of an integrated circuit. If the charges develop a high voltage that the chip cannot tolerate, a fatal discharge may happen inside the chip to cause the chip malfunction.
Most of the time, the bonding pin of the integrated circuit (IC) is the first and nearest component to interact with outside environment. The ESD protection circuit is therefore commonly placed around the bonding pins and more specifically around the IO ring of the integrated circuit. The input/output buffer is the first circuit component to connect to the bonding pins to provide interaction between internal circuit core and the outside environment. Thus, it is very important that the input and output buffers can withstand ESD events.
FIG. 1 illustrates a conventional ESD protection circuit 100 for output buffer. The ESD protection circuit 100 includes a pre-driver 101, an output buffer 102, and a circuit 103. The output buffer 102 includes a P-Channel MOSFET transistor P1 and an N-Channel MOSFET transistor N1. Two supply terminals VDD and VSS are respectively held at voltages VDD and VSS. The pre-driver 101 can provide logic functions to turn on/off the output buffer 102. One of the pre-driver implementation just consists of two inverters, respectively to buffer the output transistors. In order to turn on P-Channel MOSFET transistor P1, the logic level of PRE_PUP will be high and PUP will then be low. When PRE_NDN is low, NDN will be high after the inverter and thus turn on the N-Channel MOSFET transistor N1. Circuit 103 includes ESD clamping diodes 110 and 111.
The parasitic diodes 120 and 121 respectively associated with the transistors P1 and N1 can function as discharging diodes. During an ESD event zapping from pad 140 to VDD, positive charges can accumulate at the pad 140 and/or a negative charge can be stored at the VDD terminal. Once the electrostatic voltage developed is above the threshold of the parasitic diode 120, a discharging path is formed to allow ESD current to flow from the pad 140 through the diode 120 to the voltage supply terminal VDD. If ESD event occurs zapping from the pad 140 to the voltage supply terminal VSS, the parasitic capacitance Cgd2 formed between gate-overlapped drain capacitance in the N-Channel MOSFET transistor N1 can couple the ESD charges to develop voltage on the node NDN. Once this developed electrostatic voltage exceeds the threshold of the N-Channel MOSFET transistor N1, the N-Channel MOSFET transistor N1 is turned on to shunt ESD current. Clamping diodes 110 and 111 can be included in the ESD protection circuit 100 to provide discharge current paths from VSS to pad 140 and from pad 140 to VDD. The clamping diodes 110 and 111 are normally built from N-Channel MOSFET transistor and P-Channel MOSFET transistor with gate connected to its source.
The ESD protection circuit 100 includes several disadvantages. The parasitic diodes 120 and 121 in the ESD protection circuit 100 provide a passive ESD protection mechanism. No active circuit is present to detect an ESD event and turn on ESD protection devices. The current carrying capability of the diodes is proportional to the drawn area formed in its p-n junction. As the diodes are scaled down to sub-micro technologies, the diodes can only provide moderate ESD protection and is sometimes ineffective at all. Moreover, no logic controls are provided to keep the node PUP low and the node NDN high in response to the ESD zapping between VDD and the pad 140, and the pad 140 and VSS. That means that the transistors P1 and N1 may not be turned on in these ESD events to provide current ESD discharge paths from the supply terminal VDD to the pad 140 and the pad 140 to the supply terminal VSS in these ESD events. Additionally, the ESD protection circuit 100 is effective at the power up state during normal device operations. The output buffer 101 is normally disabled, meaning Hi-impedance state by default setting when the supply terminal VDD is powered-up in normal operation. The node PUP is normally at a high-voltage state and the P-Channel MOSFET transistor P1 is turned off.
Different conventional circuits for protecting the input and output buffers from ESD events include several disadvantages. Some conventional ESD protection circuits include clamping diodes to provide passive discharging current path. As the device is miniaturized to smaller scales, the clamping diodes can no longer provide ESD protection. As the gate oxide thickness reduces from 500 Å in 3 μm process technology to 16 Å in 0.13 μm process technology, the gate oxide layer becomes susceptible to damages by electrostatic charges. The clamping diodes in the conventional ESD protection circuits cannot be scaled to sub-micro scales. Moreover, the insertion of the clamping diodes also increases overall output buffer area. The clamping diodes in the conventional ESD protection circuits are usually implemented by N-Channel MOSFET and P-Channel MOSFET transistors. The sizes of the N-Channel MOSFET and P-Channel MOSFET transistors have to be very large for the transistors to provide enough current discharge as clamping diodes. The sizes of the transistors usually cannot scale with the reduced scale in the chip processing technologies.
Some conventional ESD protection circuits include high value resistor serially connected with the input/output buffer. A typical inserted resistor is in a range of several hundred ohms to several thousands ohms. A large resistor load like this can significantly reduce the driving capability and the switching frequency of the electronic device. These disadvantages become prevalent in high frequency and large driving current applications.
Furthermore, some conventional ESD protection circuits are disabled and cannot provide ESD protection when the electronic device is powered up. Some conventional ESD protection circuits may cause logic conflict at the output buffer, which can degrade the ESD protection circuitry. Some conventional ESD protection circuits only provide discharging path between a limited number of pad and supply terminals in restrictive directions.